1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices, and, more particularly, to the silicidation of elements of semiconductor devices, for example, gate electrodes of transistor devices, in the context of integrated formation of a variety of semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
In sophisticated transistor elements, a plurality of features finally determine the overall performance of the transistor, wherein a complex mutual interaction of these factors may be difficult to assess such that a wide variety of performance variations may be observed for a given basic transistor configuration. For example, the conductivity of doped silicon-based semiconductor regions may be increased by providing a metal silicide therein in order to reduce overall sheet resistance and contact resistivity. For example, the drain and source regions may receive a metal silicide, such as nickel silicide, nickel platinum silicide and the like, thereby reducing the overall series resistance of the conductive path between the drain and source terminals and the intermediate channel region. Similarly, a metal silicide may typically be formed in the gate electrode, which may comprise polysilicon material, thereby enhancing conductivity and thus reducing signal propagation delay. Although an increased amount of metal silicide in the gate electrode may per se be desirable in view of reducing the overall resistance thereof, a substantially complete silicidation (salicidation) of the polycrystalline silicon material down to the gate dielectric material may not be desirable in view of threshold voltage adjustment of the corresponding transistor element. It may, therefore, be desirable to maintain a certain portion of the doped polysilicon material in direct contact with the gate dielectric material so as to provide well-defined electronic characteristics in the channel region, so as to avoid significant threshold variations, which may be caused by a substantially full silicidation within portions of the gate electrode.
On the other hand, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode have been implemented that provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
In principle, there are two well-known processing methods for forming a planar or 3D transistor with a high-k/metal gate (HK/MG) structure: (1) the so-called “gate last” or “replacement gate” technique; and (2) the so-called “gate first” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed. In general, using the “gate first” technique involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer, one or more metal layers, a layer of polysilicon and a protective cap layer, e.g., silicon nitride. Thereafter, one or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices.
An example of a conventional gate last processing is illustrated in FIG. 1. In the processing stage shown, a semiconductor device comprises a replacement gate 1 covered by a cap layer 2 that was used for patterning the layer from which the replacement gate 1 was formed. The cap layer 2 may be a nitride layer, for example. Sidewall spacers 3 are formed at sides of the replacement gate. Source/drain regions 4 are formed adjacent to the sidewall spacers 3. Next, an inter-layer dielectric (ILD) 5 is formed above the structure and, after planar back polishing, the structure shown in the penultimate sketch of FIG. 1 results. Subsequently, the replacement gate 1 can be removed and a high-k layer 6 and gate electrode 7 can be formed between the sidewall spacers 3.
An example of a conventional gate first processing is illustrated in FIG. 2. A stack of layers of material across the substrate is formed, wherein the stack of materials, in principle, may include a high-k gate isolation layer, one or more metal layers, a layer of polysilicon, and a protective cap layer, for example, silicon nitride. One or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices. As shown at the top of FIG. 2, the gate structure comprises a gate electrode 10, cap layer 12 and sidewall spacers 13. The structure may comprise a high-k gate isolation layer (not shown) and the gate electrode 10 may comprise one or more metal layers and a layer of polysilicon. The protective cap layer 12 and the spacers 13 were formed to protect the gate structures from subsequent processing operations after the gates were patterned. Ion implantation in the context of an embedded SiGe sequence can be carried out in order to form source and drain regions. Subsequently, the protective cap layer 12 must be removed such that a metal silicide region 16 may be formed in the polysilicon gate material of the gate 10 so as to thereby reduce its contact resistance. In principle, a relatively thin layer of silicon dioxide may be deposited across the structure in order to protect the sidewall spacer 13 when the gate cap layer 12 is removed. After removal of the cap layer 12, silicidation is performed that results both in the metal silicide region 16 of the gate and silicidated source/drain regions 14.
It is important to note that, in general, the formation of transistor devices is part of an overall integrated processing of a variety of devices, such as transistors, fuses, resistors, etc. For example, also shown in FIG. 2 is an additional semiconductor device 18, for example, a polysilicon resistor, that has to be protected against silicidation by means of a protection (silicidation block) layer 15 formed by lithographic and etching processes.
However, in the gate last processing shown in FIG. 1, the cap layer has to be removed with a polish process. Consequently, formation of silicidated fuses formed in common fuse integration is not possible, but rather it is necessary to form vias or metal fuses, which complicated the overall formation of a finally resulting semiconductor device.
In the gate first processing shown in FIG. 2, on the other hand, the cap layer is to be removed in order to ensure gate silicidation. However, in parallel, unsilicidated other devices, such as polysilicon resistors, for example, have to be formed in a similar way as gate electrodes. Therefore, after removal of the cap layer 12 in order to allow for silicidation of the gate, an additional protection layer 15 has to be formed over resistor structures 18, thereby complicating the overall processing.
In view of the situation described above, the present disclosure provides techniques that allow for the silicidation of some devices without silicidation of other devices in the context of integrated formation of semiconductor devices without the need for complex overall processing.